Capstone Research Project · 2026
Vision Transformer
on FPGA
Designing and implementing an efficient hardware accelerator for Vision Transformer inference on reconfigurable FPGA fabric.
Overall Progress
0%
4
Team Members
4 active researchers
0/12
Tasks Done
6 in progress
7
Brainstorm Ideas
3 pinned
18
Resources
7 papers
Team Progress
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Jerry (Chenjia)
Hardware Architect
SY
Stephanie (Yixin)
ML Model Engineer
TY
Tiffany (Yiling)
HLS/RTL Developer
WN
Winnie (Weini)
Systems & Integration
Upcoming Meetings
CalendarNo upcoming meetings
Top Ideas
Brainstorm board▲9
Use INT4 mixed-precision quantization
Apply INT4 for weights and INT8 for activations to reduce model size by 2x while maintaining accuracy within 2% of FP32 baseline.
▲7
Pipelined HLS design for FFN layers
Use HLS PIPELINE pragma with II=1 to fully pipeline the feed-forward network layers, maximizing throughput.
▲6
Tile-based attention computation
Partition the attention matrix into tiles that fit in on-chip BRAM to avoid expensive DRAM accesses during the softmax computation.
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In Progress Tasks
Write HLS kernel for multi-head attention
Survey ViT model variants (DeiT, Swin, CvT)
Review papers on ViT on FPGA architecture papers