Member Progress
Track individual tasks, roles, and research notes for each team member.
JC
Jerry (Chenjia)
Hardware Architect
Progress25%
Designing the FPGA datapath, memory hierarchy, and systolic array for attention computation.
Tasks (8)
Optimize on-chip BRAM allocation
Run resource utilization synthesis
Implement systolic array for MatMul
Define top-level FPGA architecture diagram
Define top-level FPGA architecture diagram
Optimize on-chip BRAM allocation
Implement systolic array for MatMul
Run resource utilization synthesis
SY
Stephanie (Yixin)
ML Model Engineer
Progress25%
Responsible for ViT model design, quantization experiments, and accuracy benchmarking.
Tasks (8)
Benchmark accuracy vs. bit-width trade-off
Write model compression section of report
Implement INT8 post-training quantization
Survey ViT model variants (DeiT, Swin, CvT)
Write model compression section of report
Implement INT8 post-training quantization
Survey ViT model variants (DeiT, Swin, CvT)
Benchmark accuracy vs. bit-width trade-off
TY
Tiffany (Yiling)
HLS/RTL Developer
Progress0%
Writing HLS kernels and RTL modules for the attention and FFN layers.
Tasks (6)
Verify HLS vs. software golden output
Write HLS kernel for multi-head attention
Implement layer normalization in RTL
Implement layer normalization in RTL
Write HLS kernel for multi-head attention
Verify HLS vs. software golden output
WN
Winnie
Systems & Integration
Progress25%
Handling end-to-end integration, board bring-up, and performance profiling on the FPGA.
Tasks (8)
Profile latency and throughput
Integrate HLS IP cores into top-level design
Set up Vivado project and constraints
Run end-to-end inference on FPGA board
Profile latency and throughput
Set up Vivado project and constraints
Run end-to-end inference on FPGA board
Integrate HLS IP cores into top-level design