Member Progress
Track individual tasks, roles, and research notes for each team member.
JC
Jerry (Chenjia)
Hardware Architect
Progress0%
Designing the FPGA datapath, memory hierarchy, and systolic array for attention computation.
Tasks (1)
Review papers on ViT on FPGA architecture papers
SY
Stephanie (Yixin)
ML Model Engineer
Progress0%
Responsible for ViT model design, quantization experiments, and accuracy benchmarking.
Tasks (5)
Write model compression section of report
Benchmark accuracy vs. bit-width trade-off
Survey ViT model variants (DeiT, Swin, CvT)
Review papers on ViT model
Find tinest ViT model
TY
Tiffany (Yiling)
HLS/RTL Developer
Progress0%
Writing HLS kernels and RTL modules for the attention and FFN layers.
Tasks (3)
Write HLS kernel for multi-head attention
Implement layer normalization in RTL
Research FPGA kernel script for transformers
WN
Winnie (Weini)
Systems & Integration
Progress0%
Handling end-to-end integration, board bring-up, and performance profiling on the FPGA.
Tasks (3)
Integrate HLS IP cores into top-level design
Set up Vivado project and constraints
Research end-to-end implementation of vision transformer on FPGA